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RM0008
6.3.3
Low-, medium- and high-density reset and clock control (RCC)
Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CSSC
w
Reserved
PLL
RDYC
w
HSE
RDYC
w
HSI
RDYC
w
LSE
RDYC
w
LSI
RDYC
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PLL
RDYIE
rw
HSE
RDYIE
rw
HSI
RDYIE
rw
LSE
RDYIE
rw
LSI
RDYIE
rw
CSSF
r
Reserved
PLL
RDYF
r
HSE
RDYF
r
HSI
RDYF
r
LSE
RDYF
r
LSI
RDYF
r
Bits 31:24
Reserved, always read as 0.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bits 22:21
Reserved, always read as 0.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Doc ID 13902 Rev 9
87/995
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